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HM-6617/883
June 2004
2K x 8 CMOS PROM
Description
The HM-6617/883 is a 16,384-bit fuse link CMOS PROM in a 2K word by 8-bit/word format with "Three-State" outputs. The HM-6617/883 utilizes a synchronous design technique. This includes on-chip address latches and a separate output enable control which makes this device ideal for applications utilizing recent generation microprocessors. This design technique, combined with the Intersil advanced self-aligned silicon gate CMOS process technology offers ultra-low standby current. Low ICCSB is ideal for battery applications or other systems with low power requirements. The Intersil NiCr fuse link technology is utilized on this and other Intersil CMOS PROMs. This gives the user a PROM with permanent, stable storage characteristics over the full industrial and military temperature voltage ranges. NiCr fuse technology combined with the low power characteristics of CMOS provides an excellent alternative to standard bipolar PROMs or NMOS EPROMs. All bits are manufactured storing a logical "0" and can be
Features
* This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * Low Power Standby and Operating Power - ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100A - ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA at 1MHz * Fast Access Time. . . . . . . . . . . . . . . . . . . . . . . . . . 120ns * Industry Standard Pinout * Single 5.0V Supply * CMOS/TTL Compatible Inputs * High Output Drive . . . . . . . . . . . . . . . . 12 LSTTL Loads * Synchronous Operation * On-Chip Address Latches * Separate Output Enable * Operating Temperature Range . . . . . . -55oC to +125oC
Ordering Information
PACKAGE SBDIP TEMPERATURE RANGE -55oC to +125oC 120ns HM1-6617/883 PACKAGE NO. D24.6
Pinout
HM-6617/883 (SBDIP) TOP VIEW PIN
A7 A6 A5 A4 A3 A2 A1 A0 Q0 1 2 3 4 5 6 7 8 9 24 VCC 23 A8 22 A9 21 P 20 G 19 A10 18 E 17 Q7 16 Q6 15 Q5 14 Q4 13 Q3
PIN DESCRIPTION DESCRIPTION No Connect Address Inputs Chip Enable Data Output Power (+5V) Output Enable Program Enable
NC A0-A10 E Q VCC G P (Note)
Q1 10 Q2 11 GND 12
NOTE: P should be hardwired to VCC except during programming.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 2001
FN3016.3
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HM-6617/883 Functional Diagram
MSB A10 A9 A8 A7 A6 A5 A4 A LATCHED ADDRESS REGISTER A 7 LSB L G 16 16 16 16 16 16 16 16 G E GATED COLUMN DECODER AND DATA OUTPUT CONTROL A 4 G L ALL LINES POSITIVE LOGIC: ACTIVE HIGH MSB A3 A2 A1 A0 THREE-STATE BUFFERS: A HIGH OUTPUT ACTIVE ADDRESS LATCHES AND GATED DECODERS: LATCH ON FALLING EDGE OF E GATE ON FALLING EDGE OF G LATCHED ADDRESS REGISTER LSB A 4 Q6 Q7 8 Q3 Q2 7 GATED ROW DECODER 128 x 128 MATRIX Q0 Q1
128
Q4 Q5
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HM-6617/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V Typical Derating Factor . . . . . . . . . . . . 5mA/MHz Increase in ICCOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance JA JC SBDIP Package . . . . . . . . . . . . . . . . . . 48oC/W 9oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.8V Input High Voltage . . . . . . . . . . . . . . . . . . . . . . +2.4V to VCC +0.3V
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5473 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
TABLE 1. HM-6617/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS PARAMETER High Level Output Voltage Low Level Output Voltage High Impedance Output Leakage Current Input Leakage Current SYMBOL VOH1 VOL IIOZ (NOTES 1, 4) CONDITIONS VCC = 4.5V, IO = -2.0mA VCC = 4.5V, IO = +4.8mA VCC = 5.5V, G = 5.5V, VI/O = GND or VCC VCC = 5.5V, VI = GND or VCC, P Not Tested VI = VCC or GND, VCC = 5.5V, IO = 0mA VCC = 5.5V, G = GND, (Note 3), f = 1MHz, IO = 0mA, VI = VCC or GND VCC = 4.5V (Note 6) GROUP A SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC MIN 2.4 -1.0 MAX 0.4 1.0 UNITS V V A
II
1, 2, 3
-1.0
1.0
A
Standby Supply Current
ICCSB
1, 2, 3
-
100
A
Operating Supply Current
ICCOP
1, 2, 3
-
20
mA
Functional Test
FT
7, 8A, 8B
-55oC TA +125oC
-
-
TABLE 2. HM-6617/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS HM-6617/883 PARAMETER
Address Access Time Output Enable Access Time Chip Enable Access Time Address Setup Time Address Hold Time Chip Enable Low Width Chip Enable High Width
SYMBOL
TAVQV TGLQV
(NOTES 1, 2, 4) CONDITIONS
VCC = 4.5V and 5.5V (Note 5) VCC = 4.5V and 5.5V
GROUP A SUBGROUPS
9, 10, 11 9, 10, 11
TEMPERATURE
-55oC TA +125oC -55oC TA +125oC
MIN
-
MAX
140 50
UNITS
ns ns
TELQV
VCC = 4.5V and 5.5V
9, 10, 11
-55oC TA +125oC
-
120
ns
TAVEL TELAX TELEH TEHEL
VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V
9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11
-55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC
20 25 120 40
-
ns ns ns ns
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HM-6617/883
TABLE 2. HM-6617/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) Device Guaranteed and 100% Tested LIMITS HM-6617/883 PARAMETER
Read Cycle Time
SYMBOL
TELEL
(NOTES 1, 2, 4) CONDITIONS
VCC = 4.5V and 5.5V
GROUP A SUBGROUPS
9, 10, 11
TEMPERATURE
-55oC TA +125oC
MIN
160
MAX
-
UNITS
ns
NOTES: 1. All voltages referenced to Device GND. 2. AC measurements assume transition time 5ns; input levels = 0.0V to 3.0V; timing reference levels = 1.5V; output load = 1TTL equivalent load and CL 50pF. 3. Typical derating = 5mA/MHz increase in ICCOP. 4. All tests performed with P hardwired to VCC. 5. TAVQV = TELQV + TAVEL. 6. Tested as follows: f = 1MHz, VIH = 2.4V, VIL = 0.8V, IOH = -1mA, IOL = +1mA, VOH 1.5V, VOL 1.5V. TABLE 3. HM-6617/883 AC AND DC ELECTRICAL PERFORMANCE SPECIFICATIONS LIMITS HM-6617/883 PARAMETER
Input Capacitance
SYMBOL
CIN
(NOTES 1, 2) CONDITIONS
VCC = Open, f = 1MHz, All Measurements Referenced to Device GND VCC = Open, f = 1MHz, All Measurements Referenced to Device GND VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V, IO = 100A
NOTES
2
TEMPERATURE
+25oC +25oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC
MIN
-
MAX
10
UNITS
pF
I/O Capacitance
CI/O
2
-
12
pF
Chip Enable Time Output Enable Time Chip Disable Time Output Disable Time Output High Voltage
TELQX TGLQX TEHQZ TGHQZ VOH2
2 2 2 2 2
5 5 VCC1V
50 50 -
ns ns ns ns V
NOTES: 1. All tests performed with P hardwired to VCC. 2. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design changes which would affect these characteristics. TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Groups C & D METHOD 100%/5004 100%/5004 100%/5004 100%/5004 Samples/5005 Samples/5005 SUBGROUPS 1, 7, 9 1 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9
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HM-6617/883
Switching Waveforms
TAVQV VALID ADDRESS TAVEL TELAX TELEH E 1.5V TEHEL G 1.5V TGLQX TGHQZ DATA OUTPUT Q0-Q7 TELQX VALID DATA TS 1.5V TELQV TGLQV 1.5V 0V 1.5V TEHQZ 3.0V 1.5V 0V 3.0V VALID ADDRESSES TELEL 3.0V 0V
ADDRESSES
1.5V
1.5V
FIGURE 1. READ CYCLE
Test Circuit
DUT CL (NOTE)
IOH NOTE: TEST HEAD CAPACITANCE
1.5V
IOL
EQUIVALENT CIRCUIT
FIGURE 2. TEST CIRCUIT
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HM-6617/883 Burn-In Circuit
NOTES:HM-6617/883 (.600 INCH) SBDIP
VCC C f8 f7 f6 f5 f4 f3 f2 f1 1 2 3 4 5 6 7 8 9 VCC/2 A7 A6 A5 A4 A3 A2 A1 A0 Q0 VCC 24 A6 23 A5 22 P 21 G 20 A10 19 E 18 Q7 17 Q6 16 Q5 15 Q4 14 Q3 13 VCC/2 f11 f12 VCC f1 f13 f0
10 Q1 11 Q2 12 GND
GND
f0 = 100KHz 10%. All resistors = 47k Unless Otherwise Noted. VCC = 5.5V 0.05V. C = 0.01 F min.
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HM-6617/883 Die Characteristics
DIE DIMENSIONS: 140 x 232 x 19 1mils METALLIZATION: Type: Si - Al Thickness: 11kA 15kA GLASSIVATION: Type: SiO2 Thickness: 7kA 9kA WORST CASE CURRENT DENSITY: 1.7 x 105 A/cm2
Metallization Mask Layout
HM-6617/883
A4 A5 A3 A2 A6 A7 VCC A8 A9 P G A10
A1 A0 Q0 Q1 Q2 GND Q3 Q4 Q5 Q6
E Q7
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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